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| TUESDAY, June 8, 2004, 2:00 PM - 4:00 PM | Room: 6D |
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TOPIC AREA: EMBEDDED SYSTEMS
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SESSION 9
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| Performance Evaluation and Run Time Support
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| Chair: Joerg Henkel - Univ. of Karlsruhe, Karlsruhe, Germany
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| Organizers: Radu Marculescu, Rainer Leupers
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| Evaluating system performance is a critical issue in systems design. Of particular interest is performance evaluation at higher levels of abstraction. The papers in this session cover techniques ranging from WCET to run-time support for various architectures and platforms. The first two papers deal with early performance estimation. The next two propose new optimization techniques for dynamic scheduling. Finally, the last paper presents an area estimation technique for reconfigurable devices.
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| 9.1 |
Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis
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| Speaker(s): | Tobias Schuele - Univ. of Kaiserslautern, Kaiserslautern, Germany
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| Author(s): | Tobias Schuele - Univ. of Kaiserslautern, Kaiserslautern, Germany
Klaus Schneider - Univ. of Kaiserslautern, Kaiserslautern, Germany
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| 9.2 | Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration |
| Speaker(s): | Sudeep Pasricha - Univ. of California, Irvine, CA
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| Author(s): | Sudeep Pasricha - Univ. of California, Irvine, CA
Nikil Dutt - Univ. of California, Irvine, CA
Mohamed Ben-Romdhane - Conexant Systems, Inc., Newport Beach, CA
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| 9.3 | Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware |
| Speaker(s): | Javier Resano - Univ. Complutense de Madrid, Madrid, Spain
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| Author(s): | Javier Resano - Univ. Complutense de Madrid, Madrid, Spain
Diederik Verkest - IMEC, Leuven, Belgium
Daniel Mozos - Univ. Complutense de Madrid, Madrid, Spain
Francky Catthoor - IMEC, Leuven, Belgium
Serge Vernalde - IMEC, Leuven, Belgium
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| 9.4s | LODS: Locality-Oriented Dynamic Scheduling for On-Chip Multiprocessors |
| Speaker(s): | Mahmut Kandemir - Penn State Univ., University Park, PA
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| Author(s): | Mahmut Kandemir - Penn State Univ., University Park, PA
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| 9.5s | An Area Estimation Methodology for FPGA Based Designs at System-C Level |
| Speaker(s): | Carlo Brandolese - Politecnico di Milano, Milano, Italy
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| Author(s): | Carlo Brandolese - Politecnico di Milano, Milano, Italy
Fabio Salice - Politecnico di Milano, Milano, Italy
William Fornaciari - Politecnico di Milano, Milano, Italy
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